Head Office : Z.I. des Loges, rue de la Croix Blanche - 78350 Les Loges en Josas - France
Website :
• Phone : + 33 (0)619 870 560 • Fax : +33 (0)139 564 012 • Mail :
VectraWave Proprietary information subject to change without notice
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RFIC : VWA 50011 AA
VWA 50011 AAAA DS Rev 0.2
DATA SHEET
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Head Office : rue de la Croix Blanche - Immeuble LOGI – 78350 France
+ 33 (0)619 870 560
+33 (0)139 564 012
mail :
VWA 50011 AAAA DS Rev 0.2
VectraWave Proprietary inform tion subject to change without notice
September 09 p 4 /8
Measurement setup:
Nominal operation
For a nominal operation condition with a given VSET, the control loop is:
o
InRF
peak detector – high gain stage – gain control buffer –
pctrl
The PA output is coupled to the controller input
InRF
.
The signal to InRF input has to be in the 0.2 to 1Vp range. The
PA output level is controlled by the pad
pctrl
connected to the PA gain / power control pin. An external capacitor
(
typically uF) has to be connected to
CAP
to stabilize the loop. The value required depends on the PA (Pout VS gain
control) transfer function.
CAP
enable
Vset
pctrl
VCC_bg GND_bg
VCC_ctrl
Loop_on
GND_ctrl
InRF
Power control characterization
The setup used to characterize the controller itself is slightly different to the previous one. The power source is directly
applied to the controller RF input (InRF) and then the control loop is:
o
Vset – gm amplifier - high gain stage – gain control buffer –
pctrl – (x-1)
An external inverter is required (x-1) to add 180° phase into the loop and ensure the stability. As the loop is not
designed to be used this way, additional decoupling capacitors may be required as well.
In the test condition reference PA is no longer required