Head Office : Z.I. des Loges, rue de la Croix Blanche - 78350 Les Loges en Josas - France
Website :
• Phone : + 33 (0)619 870 560 • Fax : +33 (0)139 564 012 • Mail :
VectraWave Proprietary information subject to change without notice
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RFIC : VWA 50029 AA
VWA 50029 AAAA DS Rev 0.5
DATA SHEET
VWA
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Head Office : rue de la Croix Blanche - Immeuble LOGI
78350
France
+ 33 (0)619 870 560
+33 (0)139 564 012
mail :
VWA 50029 AAAA DS Rev 0.5
VectraWave Proprietary information subject to change without notice
July 2011
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Duobinary coder
VWA-28-DUO-SD
10 – 28
Gb/s
Description
The
VWA 50029 AA
chip
is a duobinary coder for high
data rate application, typically 10 to 25 (tbc) Gb/s. The
chip is designed in 0.18µm SiGe BiCMOS 150 GHz
process.
The device has two high frequency differential inputs
(
NRZ_in and Clock) and one differential high frequency
output (Duobinary_Out). The chip is 50Ω single ended
and 100Ω differential in and out. The chip can be used
single in and out.
The input data stream is synchronized by the input
clock and electrically coded to the duobinary format.
The output is a 3 level signal: a logical NRZ “0” input
always gives an analog “0V” output, as a logical “1”
input gives alternatively either “+V” or “-V” depending
on the previous “1” state.
The different parts of the chip are internally biased
using a voltage and currents reference circuit
(
Bandgap), in order to have the overall RF
characteristics of the chip, insensitive to the voltage
supply, the temperature and the process spread. An
enable input control pin is used to switch the chip ON
or OFF.
Three separate pins are used to bias the chip: one
dedicated to the reference circuit, the second for the
coder core (input buffers and coder core) and the last
for the 50Ω output driver. The 3 bias inputs can be
separately filtered / decoupled in order to optimize the
overall chip performances.
Applications
Duobinary TX
Fiber transmission
Ordering information
Part Number:
VWA 50029 AA
Main Features
SiGe BiCMOS - Ft = 150GHz
Data rate up to 25Gb/s
3
V / 480 mW typical bias @ 27°C
Single or differential input / output
Input amplitude (data and clock): 300mV pp
Output amplitude: 800mV pp diff (400mV on each
50
Ω output)
Temperature compensated
ON and OFF state through an enable pin control
Functional Block Diagram