Head Office : Z.I. des Loges, rue de la Croix Blanche - 78350 Les Loges en Josas - France
Website :
• Phone : + 33 (0)619 870 560 • Fax : +33 (0)139 564 012 • Mail :
VectraWave Proprietary information subject to change without notice
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RFIC : VWA 50030 AA
VWA 50030 AAAA DS Rev 0.3
D
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Head Office : rue de la Croix Blanche - Immeuble LOGI
78350
France
+ 33 (0)619 870 560
+33 (0)139 564 012
mail :
VWA 50030 AAAA DS Rev 0.3
VectraWave Proprietary information subject to change without notice
July 11
p 1 /6
Differential Amplifier
VWA-40-DIA-SD
DC – 40 Gb/s
Description
The
VWA 50030 AA
chip
is a limiting - high gain
differential amplifier for high data rate application,
typically 10 to 40 Gb/s. The chip is designed in 0.18µm
SiGe BiCMOS 150 GHz process.
The chip can be used in various ways:
Single ended input to differential output
transformer, by grounding through a capacitor
one of the inputs.
Limiting amplifier, using the high linear gain to
saturate the input signal.
Cross point adjustment can be done by tuning
the DC levels between the two inputs.
The amplifier is a 6 stages amplifier, giving typically
60
dB linear gain. When in saturation, the output
amplitude is 400 mV pp single ended (800 mV
differential pp).
The different parts of the chip are internally biased
using a voltage and currents reference circuit
(
Bandgap), in order to have the overall RF
characteristics of the chip (especially the output
amplitude), insensitive to the voltage supply, the
temperature and the process spread. An enable input
control pin is used to switch the chip ON or OFF.
Three separate pins are used to bias the chip: one
dedicated to the reference circuit, the second for the
amplifier core (input buffers and amplifier core) and the
last for the 50Ω output driver. The 3 bias inputs can be
separately filtered / decoupled in order to optimize the
overall chip performances.
Applications
Limiter.
Single to differential transformation.
Cross point control.
Ordering information
Part Number:
VWA 50030 AA
Main Features
SiGe BiCMOS - Ft = 150GHz
Data rate up to 25Gb/s
3
V / 480 mW typical bias @ 27°C
Single or differential input / output
Input amplitude: 300mV pp
Output amplitude: 800mV pp diff (400mV on each
50
Ω output)
Temperature compensated
ON and OFF state through an enable pin control
Functional Block Diagram